Business-code/fpga/rtl/rtl.al

<?xml version="1.0" encoding="UTF-8"?>
<Project>
    <Project_Created_Time>2026-08-19 14:45:50</Project_Created_Time>
    <TD_Version>4.6.96021</TD_Version>
    <UCode>11001001</UCode>
    <Name>rtl</Name>
    <HardWare>
        <Family>EF2</Family>
        <Device>EF2L45BG256B</Device>
    </HardWare>
    <Source_Files>
        <Header>
            <File>trace_build_id.vh</File>
        </Header>
        <Verilog>
            <File>motor_controller_hil.v</File>
            <File>motor_feedback_rx.v</File>
            <File>reset_sync.v</File>
            <File>top_ef2l45_motor_hil_trace.v</File>
            <File>trace_capture_ram.v</File>
            <File>trace_packet_tx.v</File>
            <File>uart_rx.v</File>
            <File>uart_tx.v</File>
        </Verilog>
        <ADC_FILE>../constraints/ef2l45_motor_hil_trace.adc</ADC_FILE>
        <SDC_FILE>../constraints/ef2l45_motor_hil_trace.sdc</SDC_FILE>
        <CWC_FILE/>
    </Source_Files>
    <TOP_MODULE>
        <LABEL/>
        <MODULE>top_ef2l45_motor_hil_trace</MODULE>
        <CREATEINDEX>auto</CREATEINDEX>
    </TOP_MODULE>
    <Project_Settings>
        <Step_Last_Change>2026-09-02 18:01:14</Step_Last_Change>
        <Current_Step>60</Current_Step>
        <Step_Status>true</Step_Status>
    </Project_Settings>
</Project>