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@@ -1,279 +0,0 @@
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-ef2_4
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-13 23 409 3264 88580 0 0
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-30.168 0.163 top_ef2l45_motor_hil_trace ef2_4 EF2L45BG256B Detail 7 1
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-clock: sys_clk
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-13 88580 3264 4
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-Setup check
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-23 3
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-Endpoint: _al_u1796|u_motor_controller/reg0_b1
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-23 30.168000 470 3
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-Timing path: u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk->_al_u1796|u_motor_controller/reg0_b1
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-u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk
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-_al_u1796|u_motor_controller/reg0_b1
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-25 30.168000 42.165000 11.997000 9 9
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-motor_state_id[10] _al_u1652|_al_u1421.a[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1737|_al_u1894.b[1]
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-_al_u1737_o _al_u1739|_al_u1738.d[1]
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-u_motor_controller/sel0_b14/B5 _al_u1741|_al_u1781.a[1]
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-_al_u1741_o _al_u1796|u_motor_controller/reg0_b1.c[1]
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-_al_u1796_o _al_u1799.a[1]
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-_al_u1799_o _al_u1796|u_motor_controller/reg0_b1.d[0]
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-
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-Timing path: u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk->_al_u1796|u_motor_controller/reg0_b1
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-u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk
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-_al_u1796|u_motor_controller/reg0_b1
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-67 30.168000 42.165000 11.997000 9 9
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-motor_state_id[10] _al_u1652|_al_u1421.a[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1737|_al_u1894.b[1]
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-_al_u1737_o _al_u1739|_al_u1738.d[1]
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-u_motor_controller/sel0_b14/B5 _al_u1741|_al_u1781.a[1]
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-_al_u1741_o _al_u1796|u_motor_controller/reg0_b1.c[1]
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-_al_u1796_o _al_u1799.a[0]
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-_al_u1799_o _al_u1796|u_motor_controller/reg0_b1.d[0]
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-
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-Timing path: u_motor_controller/reg5_b12|u_motor_controller/reg5_b5.clk->_al_u1796|u_motor_controller/reg0_b1
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-u_motor_controller/reg5_b12|u_motor_controller/reg5_b5.clk
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-_al_u1796|u_motor_controller/reg0_b1
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-109 30.179000 42.165000 11.986000 9 9
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-motor_state_id[12] _al_u1652|_al_u1421.c[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1737|_al_u1894.b[1]
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-_al_u1737_o _al_u1739|_al_u1738.d[1]
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-u_motor_controller/sel0_b14/B5 _al_u1741|_al_u1781.a[1]
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-_al_u1741_o _al_u1796|u_motor_controller/reg0_b1.c[1]
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-_al_u1796_o _al_u1799.a[1]
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-_al_u1799_o _al_u1796|u_motor_controller/reg0_b1.d[0]
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-
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-
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-Endpoint: u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-151 30.241000 394 3
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-Timing path: u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk->u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk
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-u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-153 30.241000 42.165000 11.924000 9 9
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-motor_state_id[10] _al_u1652|_al_u1421.a[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1655|u_motor_controller/reg5_b3.a[1]
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-u_motor_controller/n6_lutinv _al_u1745|_al_u1656.a[0]
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-u_trace_ram/u7_sel_is_2_o _al_u1784|u_motor_controller/reg5_b8.c[1]
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-_al_u1784_o _al_u1924|_al_u1923.b[1]
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-_al_u1924_o _al_u1941.a[1]
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-_al_u1941_o u_motor_controller/reg4_b1|u_motor_controller/reg4_b6.b[1]
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-
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-Timing path: u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk->u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk
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-u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-195 30.241000 42.165000 11.924000 9 9
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-motor_state_id[10] _al_u1652|_al_u1421.a[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1655|u_motor_controller/reg5_b3.a[1]
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-u_motor_controller/n6_lutinv _al_u1745|_al_u1656.a[0]
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-u_trace_ram/u7_sel_is_2_o _al_u1784|u_motor_controller/reg5_b8.c[1]
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-_al_u1784_o _al_u1924|_al_u1923.b[1]
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-_al_u1924_o _al_u1941.a[0]
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-_al_u1941_o u_motor_controller/reg4_b1|u_motor_controller/reg4_b6.b[1]
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-
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-Timing path: u_motor_controller/reg5_b12|u_motor_controller/reg5_b5.clk->u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-u_motor_controller/reg5_b12|u_motor_controller/reg5_b5.clk
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-u_motor_controller/reg4_b1|u_motor_controller/reg4_b6
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-237 30.252000 42.165000 11.913000 9 9
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-motor_state_id[12] _al_u1652|_al_u1421.c[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1655|u_motor_controller/reg5_b3.a[1]
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-u_motor_controller/n6_lutinv _al_u1745|_al_u1656.a[0]
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-u_trace_ram/u7_sel_is_2_o _al_u1784|u_motor_controller/reg5_b8.c[1]
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-_al_u1784_o _al_u1924|_al_u1923.b[1]
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-_al_u1924_o _al_u1941.a[1]
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-_al_u1941_o u_motor_controller/reg4_b1|u_motor_controller/reg4_b6.b[1]
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-
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-
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-Endpoint: u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-279 30.332000 390 3
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-Timing path: u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk->u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk
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-u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-281 30.332000 42.165000 11.833000 9 9
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-motor_state_id[10] _al_u1652|_al_u1421.a[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1655|u_motor_controller/reg5_b3.a[1]
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-u_motor_controller/n6_lutinv _al_u1745|_al_u1656.a[0]
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-u_trace_ram/u7_sel_is_2_o _al_u1784|u_motor_controller/reg5_b8.c[1]
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-_al_u1784_o _al_u1924|_al_u1923.b[1]
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-_al_u1924_o _al_u1943.a[1]
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-_al_u1943_o u_motor_controller/reg4_b0|u_motor_controller/reg4_b7.c[1]
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-
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-Timing path: u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk->u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-u_motor_controller/reg5_b10|u_motor_controller/reg5_b7.clk
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-u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-323 30.332000 42.165000 11.833000 9 9
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-motor_state_id[10] _al_u1652|_al_u1421.a[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1655|u_motor_controller/reg5_b3.a[1]
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-u_motor_controller/n6_lutinv _al_u1745|_al_u1656.a[0]
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-u_trace_ram/u7_sel_is_2_o _al_u1784|u_motor_controller/reg5_b8.c[1]
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-_al_u1784_o _al_u1924|_al_u1923.b[1]
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-_al_u1924_o _al_u1943.a[0]
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-_al_u1943_o u_motor_controller/reg4_b0|u_motor_controller/reg4_b7.c[1]
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-
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-Timing path: u_motor_controller/reg5_b12|u_motor_controller/reg5_b5.clk->u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-u_motor_controller/reg5_b12|u_motor_controller/reg5_b5.clk
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-u_motor_controller/reg4_b0|u_motor_controller/reg4_b7
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-365 30.343000 42.165000 11.822000 9 9
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-motor_state_id[12] _al_u1652|_al_u1421.c[1]
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-_al_u1652_o _al_u1653|u_packet_tx/reg1_b5.a[1]
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-_al_u1653_o _al_u1654|u_motor_controller/reg5_b9.e[1]
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-_al_u1654_o _al_u1655|u_motor_controller/reg5_b3.a[1]
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-u_motor_controller/n6_lutinv _al_u1745|_al_u1656.a[0]
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-u_trace_ram/u7_sel_is_2_o _al_u1784|u_motor_controller/reg5_b8.c[1]
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-_al_u1784_o _al_u1924|_al_u1923.b[1]
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-_al_u1924_o _al_u1943.a[1]
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-_al_u1943_o u_motor_controller/reg4_b0|u_motor_controller/reg4_b7.c[1]
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-
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-
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-
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-Hold check
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-407 3
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-Endpoint: u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-409 0.163000 56 3
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-Timing path: reg11_b14|reg12_b4.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-reg11_b14|reg12_b4.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-411 0.163000 2.349000 2.512000 1 1
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-fb_rpm_l[4] u_trace_ram/ram_mem0_1024x64_sub_000000_018.dib[6]
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-
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-Timing path: reg11_b4|reg12_b1.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-reg11_b4|reg12_b1.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-437 0.172000 2.349000 2.521000 1 1
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-fb_rpm_l[1] u_trace_ram/ram_mem0_1024x64_sub_000000_018.dib[3]
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-
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-Timing path: reg11_b13|reg12_b5.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-reg11_b13|reg12_b5.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_018
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-463 0.229000 2.349000 2.578000 1 1
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-fb_rpm_l[5] u_trace_ram/ram_mem0_1024x64_sub_000000_018.dib[7]
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-
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-
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-Endpoint: u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-489 0.172000 14 3
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-Timing path: reg7_b0|reg7_b5.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-reg7_b0|reg7_b5.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-491 0.172000 2.349000 2.521000 1 1
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-dump_index[5] u_trace_ram/ram_mem0_1024x64_sub_000000_027.addra[8]
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-
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-Timing path: reg7_b0|reg7_b5.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-reg7_b0|reg7_b5.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-517 0.183000 2.349000 2.532000 1 1
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-dump_index[0] u_trace_ram/ram_mem0_1024x64_sub_000000_027.addra[3]
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-
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-Timing path: reg7_b3.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-reg7_b3.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_027
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-543 0.337000 2.349000 2.686000 1 1
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-dump_index[3] u_trace_ram/ram_mem0_1024x64_sub_000000_027.addra[6]
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-
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-
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-Endpoint: u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-569 0.280000 56 3
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-Timing path: reg13_b12|reg13_b6.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-reg13_b12|reg13_b6.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-571 0.280000 2.349000 2.629000 1 1
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-fb_current_l[6] u_trace_ram/ram_mem0_1024x64_sub_000000_000.dib[7]
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-
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-Timing path: reg13_b11|reg13_b7.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-reg13_b11|reg13_b7.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-597 0.280000 2.349000 2.629000 1 1
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-fb_current_l[7] u_trace_ram/ram_mem0_1024x64_sub_000000_000.dib[8]
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-
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-Timing path: reg13_b15|reg13_b3.clk->u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-reg13_b15|reg13_b3.clk
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-u_trace_ram/ram_mem0_1024x64_sub_000000_000
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-623 0.293000 2.349000 2.642000 1 1
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-fb_current_l[3] u_trace_ram/ram_mem0_1024x64_sub_000000_000.dib[4]
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-
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-
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-
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-Recovery check
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-649 3
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-Endpoint: reg14_b21|reg14_b25
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-651 37.031000 1 1
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-Timing path: u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk->reg14_b21|reg14_b25
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-u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk
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-reg14_b21|reg14_b25
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-653 37.031000 41.981000 4.950000 1 1
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-rst_n reg14_b21|reg14_b25.sr
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-
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-
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-Endpoint: reg4_b19|reg4_b26
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-679 37.059000 1 1
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-Timing path: u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk->reg4_b19|reg4_b26
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-u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk
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-reg4_b19|reg4_b26
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-681 37.059000 41.981000 4.922000 1 1
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-rst_n reg4_b19|reg4_b26.sr
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-
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-
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-Endpoint: u_feedback_rx/reg10_b15|u_feedback_rx/reg9_b6
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-707 37.151000 1 1
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-Timing path: u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk->u_feedback_rx/reg10_b15|u_feedback_rx/reg9_b6
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-u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk
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-u_feedback_rx/reg10_b15|u_feedback_rx/reg9_b6
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-709 37.151000 41.981000 4.830000 1 1
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-rst_n u_feedback_rx/reg10_b15|u_feedback_rx/reg9_b6.sr
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-
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-
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-
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-Removal check
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-735 3
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-Endpoint: _al_u1097|reg0_b31
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-737 0.251000 1 1
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-Timing path: u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk->_al_u1097|reg0_b31
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-u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk
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-_al_u1097|reg0_b31
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-739 0.251000 2.449000 2.700000 1 1
|
|
|
-rst_n _al_u1097|reg0_b31.sr
|
|
|
-
|
|
|
-
|
|
|
-Endpoint: _al_u1497|u_packet_tx/u_uart_tx/reg0_b1
|
|
|
-765 0.312000 1 1
|
|
|
-Timing path: u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk->_al_u1497|u_packet_tx/u_uart_tx/reg0_b1
|
|
|
-u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk
|
|
|
-_al_u1497|u_packet_tx/u_uart_tx/reg0_b1
|
|
|
-767 0.312000 2.388000 2.700000 1 1
|
|
|
-rst_n _al_u1497|u_packet_tx/u_uart_tx/reg0_b1.sr
|
|
|
-
|
|
|
-
|
|
|
-Endpoint: u_packet_tx/u_uart_tx/reg0_b13|u_packet_tx/u_uart_tx/reg0_b2
|
|
|
-793 0.379000 1 1
|
|
|
-Timing path: u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk->u_packet_tx/u_uart_tx/reg0_b13|u_packet_tx/u_uart_tx/reg0_b2
|
|
|
-u_reset_sync/reg0_b0|u_reset_sync/reg0_b1.clk
|
|
|
-u_packet_tx/u_uart_tx/reg0_b13|u_packet_tx/u_uart_tx/reg0_b2
|
|
|
-795 0.379000 2.449000 2.828000 1 1
|
|
|
-rst_n u_packet_tx/u_uart_tx/reg0_b13|u_packet_tx/u_uart_tx/reg0_b2.sr
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
-
|
|
|
-Timing group statistics:
|
|
|
- Clock constraints:
|
|
|
- Clock Name Min Period Max Freq Skew Fanout TNS
|
|
|
- sys_clk (25.000MHz) 9.832ns 101.709MHz 0.281ns 541 0.000ns
|
|
|
- Minimum input arrival time before clock: no constraint path
|
|
|
- Maximum output required time after clock: no constraint path
|
|
|
- Maximum combinational path delay: no constraint path
|
|
|
-
|
botao